Hardware implementation of a Turbo Code with 3 Dimensions on FPGA

Recent wireless communication standards such as 3GPP-LTE, WiMax, DVB-SH, HSPA and LTE / LTE advanced incorporate turbo code for their excellent performance. In this paper, we present a new 3 dimensional turbo decoder including bit error rate (BER) is much better than the 2 dimensional turbo decoder used by LTE / LTE advanced, as is illustrated by simulation. We also address the issue of the implementation of the 3 dimensional turbo decoder on FPGA using the environment QUARTUS II. In this work, we also present the implementation on FPGA of 3 dimensional Turbo encoder using two interleavers QPP (Quadratic Permutation Polynomial) and ARP (Almost Regular Rotation). In decoding scheme, the core of the iterative decoding structure is a soft-input soft-output (SISO) decoder. The MAP algorithm, which is used for SISO decoders, embodies complex mathematical operations such as division, exponential and logarithm calculations. Therefore, MAP algorithm was avoided and the sub-optimal derivatives of this algorithm such as LogMAP and Max-Log-MAP were preferred for turbo decoder implementations. Keywords— 3 dimensional turbo encoder, QPP interleaver, ARP interleaver, MAP algorithm, Log max MAP, SISO decoder, 3 dimensional turbo-decoder, FPGA